[PATCH v13 07/12] PCI: Add generic domain handling

[Liviu Dudau]

From: Catalin Marinas <***@arm.com>

The handling of PCI domains (or PCI segments in ACPI speak) is usually a
straightforward affair but its implementation is currently left to the
architectural code, with pci_domain_nr(b) querying the value of the domain
associated with bus b.

This patch introduces CONFIG_PCI_DOMAINS_GENERIC as an option that can be
selected if an architecture wants a simple implementation where the value
of the domain associated with a bus is stored in struct pci_bus.

The architectures that select CONFIG_PCI_DOMAINS_GENERIC will then have to
implement pci_bus_assign_domain_nr() as a way of setting the domain number
associated with a root bus. All child buses except the root bus will
inherit the domain_nr value from their parent.

Signed-off-by: Catalin Marinas <***@arm.com>
[Renamed pci_set_domain_nr() to pci_bus_assign_domain_nr()]
Signed-off-by: Liviu Dudau <***@arm.com>
Signed-off-by: Bjorn Helgaas <***@google.com>
CC: Arnd Bergmann <***@arndb.de>
---
drivers/pci/probe.c | 11 ++++++++---
include/linux/pci.h | 21 +++++++++++++++++++++
2 files changed, 29 insertions(+), 3 deletions(-)

diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c
index e3cf8a2..636d1c9 100644
--- a/drivers/pci/probe.c
+++ b/drivers/pci/probe.c
@@ -485,7 +485,7 @@ void pci_read_bridge_bases(struct pci_bus *child)
}
}

-static struct pci_bus *pci_alloc_bus(void)
+static struct pci_bus *pci_alloc_bus(struct pci_bus *parent)
{
struct pci_bus *b;

@@ -500,6 +500,10 @@ static struct pci_bus *pci_alloc_bus(void)
INIT_LIST_HEAD(&b->resources);
b->max_bus_speed = PCI_SPEED_UNKNOWN;
b->cur_bus_speed = PCI_SPEED_UNKNOWN;
+#ifdef CONFIG_PCI_DOMAINS_GENERIC
+ if (parent)
+ b->domain_nr = parent->domain_nr;
+#endif
return b;
}

@@ -671,7 +675,7 @@ static struct pci_bus *pci_alloc_child_bus(struct pci_bus *parent,
/*
* Allocate a new bus, and inherit stuff from the parent..
*/
- child = pci_alloc_bus();
+ child = pci_alloc_bus(parent);
if (!child)
return NULL;

@@ -1761,13 +1765,14 @@ struct pci_bus *pci_create_root_bus(struct device *parent, int bus,
char bus_addr[64];
char *fmt;

- b = pci_alloc_bus();
+ b = pci_alloc_bus(NULL);
if (!b)
return NULL;

b->sysdata = sysdata;
b->ops = ops;
b->number = b->busn_res.start = bus;
+ pci_bus_assign_domain_nr(b, parent);
b2 = pci_find_bus(pci_domain_nr(b), bus);
if (b2) {
/* If we already got to this bus through a different bridge, ignore it */
diff --git a/include/linux/pci.h b/include/linux/pci.h
index 61978a4..a494e5d 100644
--- a/include/linux/pci.h
+++ b/include/linux/pci.h
@@ -456,6 +456,9 @@ struct pci_bus {
unsigned char primary; /* number of primary bridge */
unsigned char max_bus_speed; /* enum pci_bus_speed */
unsigned char cur_bus_speed; /* enum pci_bus_speed */
+#ifdef CONFIG_PCI_DOMAINS_GENERIC
+ int domain_nr;
+#endif

char name[48];

@@ -1288,6 +1291,24 @@ static inline int pci_domain_nr(struct pci_bus *bus) { return 0; }
static inline int pci_proc_domain(struct pci_bus *bus) { return 0; }
#endif /* CONFIG_PCI_DOMAINS */

+/*
+ * Generic implementation for PCI domain support. If your
+ * architecture does not need custom management of PCI
+ * domains then this implementation will be used
+ */
+#ifdef CONFIG_PCI_DOMAINS_GENERIC
+static inline int pci_domain_nr(struct pci_bus *bus)
+{
+ return bus->domain_nr;
+}
+void pci_bus_assign_domain_nr(struct pci_bus *bus, struct device *parent);
+#else
+static inline void pci_bus_assign_domain_nr(struct pci_bus *bus,
+ struct device *parent)
+{
+}
+#endif
+
/* some architectures require additional setup to direct VGA traffic */
typedef int (*arch_set_vga_state_t)(struct pci_dev *pdev, bool decode,
unsigned int command_bits, u32 flags);

[Liviu Dudau]

If the firmware has not assigned all the bus resources and we are not just
probing the PCI buses, it makes sense to assign the unassigned resources
in pci_scan_root_bus().

Signed-off-by: Liviu Dudau <***@arm.com>
Signed-off-by: Bjorn Helgaas <***@google.com>
CC: Arnd Bergmann <***@arndb.de>
CC: Jason Gunthorpe <***@obsidianresearch.com>
CC: Rob Herring <robh+***@kernel.org>
---
drivers/pci/probe.c | 3 +++
1 file changed, 3 insertions(+)

diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c
index 636d1c9..d2ebd49 100644
--- a/drivers/pci/probe.c
+++ b/drivers/pci/probe.c
@@ -1951,6 +1951,9 @@ struct pci_bus *pci_scan_root_bus(struct device *parent, int bus,
if (!found)
pci_bus_update_busn_res_end(b, max);

+ if (!pci_has_flag(PCI_PROBE_ONLY))
+ pci_assign_unassigned_bus_resources(b);
+
pci_bus_add_devices(b);
return b;
}

[Yinghai Lu]

Post by Liviu Dudau
If the firmware has not assigned all the bus resources and we are not just
probing the PCI buses, it makes sense to assign the unassigned resources
in pci_scan_root_bus().
---
drivers/pci/probe.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c
index 636d1c9..d2ebd49 100644
--- a/drivers/pci/probe.c
+++ b/drivers/pci/probe.c
@@ -1951,6 +1951,9 @@ struct pci_bus *pci_scan_root_bus(struct device *parent, int bus,
if (!found)
pci_bus_update_busn_res_end(b, max);
+ if (!pci_has_flag(PCI_PROBE_ONLY))
+ pci_assign_unassigned_bus_resources(b);
+
pci_bus_add_devices(b);
return b;
}

No, you can not do it that early.

On x86, we need to call
pcibios_resource_survey_bus at first.

Thanks

Yinghai

[Yinghai Lu]

Post by Yinghai Lu

Post by Liviu Dudau
If the firmware has not assigned all the bus resources and we are not just
probing the PCI buses, it makes sense to assign the unassigned resources
in pci_scan_root_bus().
---
drivers/pci/probe.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c
index 636d1c9..d2ebd49 100644
--- a/drivers/pci/probe.c
+++ b/drivers/pci/probe.c
@@ -1951,6 +1951,9 @@ struct pci_bus *pci_scan_root_bus(struct device *parent, int bus,
if (!found)
pci_bus_update_busn_res_end(b, max);
+ if (!pci_has_flag(PCI_PROBE_ONLY))
+ pci_assign_unassigned_bus_resources(b);
+
pci_bus_add_devices(b);
return b;
}

No, you can not do it that early.
On x86, we need to call
pcibios_resource_survey_bus at first.

on x86:
pcibios_init
pcibios_resource_survey()
pcibios_assign_resources() via fs_initcall

[Benjamin Herrenschmidt]

Post by Yinghai Lu

Post by Yinghai Lu

Post by Liviu Dudau
If the firmware has not assigned all the bus resources and we are not just
probing the PCI buses, it makes sense to assign the unassigned resources
in pci_scan_root_bus().
---
drivers/pci/probe.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c
index 636d1c9..d2ebd49 100644
--- a/drivers/pci/probe.c
+++ b/drivers/pci/probe.c
@@ -1951,6 +1951,9 @@ struct pci_bus *pci_scan_root_bus(struct device *parent, int bus,
if (!found)
pci_bus_update_busn_res_end(b, max);
+ if (!pci_has_flag(PCI_PROBE_ONLY))
+ pci_assign_unassigned_bus_resources(b);
+
pci_bus_add_devices(b);
return b;
}

No, you can not do it that early.
On x86, we need to call
pcibios_resource_survey_bus at first.

pcibios_init
pcibios_resource_survey()
pcibios_assign_resources() via fs_initcall

Right and on powerpc and others as well. We need to survey existing
resources. We also have a number of platform things that might need
to happen before we do the final re-assignment pass.

Ben.

[Bjorn Helgaas]

On Mon, Sep 29, 2014 at 3:02 PM, Benjamin Herrenschmidt

Post by Benjamin Herrenschmidt

Post by Yinghai Lu

Post by Yinghai Lu

Post by Liviu Dudau
If the firmware has not assigned all the bus resources and we are not just
probing the PCI buses, it makes sense to assign the unassigned resources
in pci_scan_root_bus().
---
drivers/pci/probe.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c
index 636d1c9..d2ebd49 100644
--- a/drivers/pci/probe.c
+++ b/drivers/pci/probe.c
@@ -1951,6 +1951,9 @@ struct pci_bus *pci_scan_root_bus(struct device *parent, int bus,
if (!found)
pci_bus_update_busn_res_end(b, max);
+ if (!pci_has_flag(PCI_PROBE_ONLY))
+ pci_assign_unassigned_bus_resources(b);
+
pci_bus_add_devices(b);
return b;
}

No, you can not do it that early.
On x86, we need to call
pcibios_resource_survey_bus at first.

pcibios_init
pcibios_resource_survey()
pcibios_assign_resources() via fs_initcall

Right and on powerpc and others as well. We need to survey existing
resources. We also have a number of platform things that might need
to happen before we do the final re-assignment pass.

That's true today. But I don't know whether it *has* to be this way
forever. On x86, pcibios_resource_survey() throws in E820 information
(which we know long before we do any PCI enumeration) and some IO-APIC
resources (it looks like we also know these before PCI enumeration).
Powerpc has pcibios_reserve_legacy_regions(), but that looks like
mostly stuff that could be done when we find the host bridge, before
we enumerate PCI devices below it.

Bjorn

[Benjamin Herrenschmidt]

Post by Bjorn Helgaas

Post by Benjamin Herrenschmidt
Right and on powerpc and others as well. We need to survey existing
resources. We also have a number of platform things that might need
to happen before we do the final re-assignment pass.

That's true today. But I don't know whether it *has* to be this way
forever. On x86, pcibios_resource_survey() throws in E820 information
(which we know long before we do any PCI enumeration) and some IO-APIC
resources (it looks like we also know these before PCI enumeration).
Powerpc has pcibios_reserve_legacy_regions(), but that looks like
mostly stuff that could be done when we find the host bridge, before
we enumerate PCI devices below it.

Oh we can probably change that but it's going to be much more work than
just moving the assignment into pci_scan_root_bus(). There are also a
number of subtle and not-so-subtle bits of code that rely on side
effects of the current code such as anything that tests for bus->added
or dev->added. Again, nothing we can't sort out eventually but the
transition might be a bit painful.

We might need to introduce a new flag for platforms converted to the
"new style" generalized resource assignment which we can deprecate once
everybody has moved over.

Cheers,
Ben.

[Bjorn Helgaas]

On Mon, Sep 29, 2014 at 4:31 PM, Benjamin Herrenschmidt

Post by Benjamin Herrenschmidt

Post by Bjorn Helgaas

Post by Benjamin Herrenschmidt
Right and on powerpc and others as well. We need to survey existing
resources. We also have a number of platform things that might need
to happen before we do the final re-assignment pass.

That's true today. But I don't know whether it *has* to be this way
forever. On x86, pcibios_resource_survey() throws in E820 information
(which we know long before we do any PCI enumeration) and some IO-APIC
resources (it looks like we also know these before PCI enumeration).
Powerpc has pcibios_reserve_legacy_regions(), but that looks like
mostly stuff that could be done when we find the host bridge, before
we enumerate PCI devices below it.

Oh we can probably change that but it's going to be much more work than
just moving the assignment into pci_scan_root_bus().

Agreed. It's obvious that we can't apply Liviu's patch as-is.

Post by Benjamin Herrenschmidt
There are also a
number of subtle and not-so-subtle bits of code that rely on side
effects of the current code such as anything that tests for bus->added
or dev->added. Again, nothing we can't sort out eventually but the
transition might be a bit painful.
We might need to introduce a new flag for platforms converted to the
"new style" generalized resource assignment which we can deprecate once
everybody has moved over.

There's definitely a lot of work here if we ever want to make this happen.

Bjorn

[Liviu Dudau]

Post by Bjorn Helgaas
On Mon, Sep 29, 2014 at 4:31 PM, Benjamin Herrenschmidt

Right and on powerpc and others as well. We need to survey exist=

ing

Post by Bjorn Helgaas

resources. We also have a number of platform things that might n=

eed

Post by Bjorn Helgaas

to happen before we do the final re-assignment pass.

That's true today. But I don't know whether it *has* to be this w=

ay

Post by Bjorn Helgaas

forever. On x86, pcibios_resource_survey() throws in E820 informa=

tion

Post by Bjorn Helgaas

(which we know long before we do any PCI enumeration) and some IO-=

APIC

Post by Bjorn Helgaas

resources (it looks like we also know these before PCI enumeration=

).

Post by Bjorn Helgaas

Powerpc has pcibios_reserve_legacy_regions(), but that looks like
mostly stuff that could be done when we find the host bridge, befo=

re

Post by Bjorn Helgaas

we enumerate PCI devices below it.

Oh we can probably change that but it's going to be much more work =

than

Post by Bjorn Helgaas

just moving the assignment into pci_scan_root_bus().

=20
Agreed. It's obvious that we can't apply Liviu's patch as-is.

Thanks everyone for the feedback!

Bjorn, you can drop this patch from the series if you want to add it to
your tree, and the host bridge drivers will have to reimplement pci_sca=
n_root_bus()
for now (most do it already as they need to add msi information as well=
).

Benjamin, I still have on my ToDo list to convert powerpc. I might not =
be
able to do it successfully on my own (as I don't understand a lot of th=
e
corner cases) but Bjorn is correct here in that pcibios_reserve_legacy_=
regions()
will move out of the scanning of the root bus.

Post by Bjorn Helgaas
=20

There are also a
number of subtle and not-so-subtle bits of code that rely on side
effects of the current code such as anything that tests for bus->ad=

ded

Post by Bjorn Helgaas

or dev->added. Again, nothing we can't sort out eventually but the
transition might be a bit painful.
We might need to introduce a new flag for platforms converted to th=

e

Post by Bjorn Helgaas

"new style" generalized resource assignment which we can deprecate =

once

Post by Bjorn Helgaas

everybody has moved over.

=20
There's definitely a lot of work here if we ever want to make this ha=

ppen.

I know :)

Best regards,
Liviu

Post by Bjorn Helgaas
=20
Bjorn
=20

--=20
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
| I would like to |
| fix the world, |
| but they're not |
| giving me the |
\ source code! /
---------------
=C2=AF\_(=E3=83=84)_/=C2=AF

[Liviu Dudau]

Add pci_get_new_domain_nr() to allocate a new domain number and
of_get_pci_domain_nr() to retrieve the PCI domain number of a given device
from DT. Host bridge drivers or architecture-specific code can choose to
implement their PCI domain number policy using these two functions.

Using of_get_pci_domain_nr() guarantees a stable PCI domain number on every
boot provided that all host bridge controllers are assigned a number in the
device tree using "linux,pci-domain" property. Mixing use of
pci_get_new_domain_nr() and of_get_pci_domain_nr() is not recommended as it
can lead to potentially conflicting domain numbers being assigned to root
buses behind different host bridges.

Signed-off-by: Liviu Dudau <***@arm.com>
Signed-off-by: Bjorn Helgaas <***@google.com>
CC: Arnd Bergmann <***@arndb.de>
CC: Grant Likely <***@linaro.org>
CC: Rob Herring <robh+***@kernel.org>
CC: Catalin Marinas <***@arm.com>
---
drivers/of/of_pci.c | 25 +++++++++++++++++++++++++
drivers/pci/pci.c | 9 +++++++++
include/linux/of_pci.h | 7 +++++++
include/linux/pci.h | 3 +++
4 files changed, 44 insertions(+)

diff --git a/drivers/of/of_pci.c b/drivers/of/of_pci.c
index 8481996..82d172f 100644
--- a/drivers/of/of_pci.c
+++ b/drivers/of/of_pci.c
@@ -89,6 +89,31 @@ int of_pci_parse_bus_range(struct device_node *node, struct resource *res)
}
EXPORT_SYMBOL_GPL(of_pci_parse_bus_range);

+/**
+ * This function will try to obtain the host bridge domain number by
+ * finding a property called "linux,pci-domain" of the given device node.
+ *
+ * @node: device tree node with the domain information
+ *
+ * Returns the associated domain number from DT in the range [0-0xffff], or
+ * a negative value if the required property is not found.
+ */
+int of_get_pci_domain_nr(struct device_node *node)
+{
+ const __be32 *value;
+ int len;
+ u16 domain;
+
+ value = of_get_property(node, "linux,pci-domain", &len);
+ if (!value || len < sizeof(*value))
+ return -EINVAL;
+
+ domain = (u16)be32_to_cpup(value);
+
+ return domain;
+}
+EXPORT_SYMBOL_GPL(of_get_pci_domain_nr);
+
#ifdef CONFIG_PCI_MSI

static LIST_HEAD(of_pci_msi_chip_list);
diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c
index 2c9ac70..d36f35f 100644
--- a/drivers/pci/pci.c
+++ b/drivers/pci/pci.c
@@ -4406,6 +4406,15 @@ static void pci_no_domains(void)
#endif
}

+#ifdef CONFIG_PCI_DOMAINS
+static atomic_t __domain_nr = ATOMIC_INIT(-1);
+
+int pci_get_new_domain_nr(void)
+{
+ return atomic_inc_return(&__domain_nr);
+}
+#endif
+
/**
* pci_ext_cfg_avail - can we access extended PCI config space?
*
diff --git a/include/linux/of_pci.h b/include/linux/of_pci.h
index dde3a4a..71062e9 100644
--- a/include/linux/of_pci.h
+++ b/include/linux/of_pci.h
@@ -15,6 +15,7 @@ struct device_node *of_pci_find_child_device(struct device_node *parent,
int of_pci_get_devfn(struct device_node *np);
int of_irq_parse_and_map_pci(const struct pci_dev *dev, u8 slot, u8 pin);
int of_pci_parse_bus_range(struct device_node *node, struct resource *res);
+int of_get_pci_domain_nr(struct device_node *node);
#else
static inline int of_irq_parse_pci(const struct pci_dev *pdev, struct of_phandle_args *out_irq)
{
@@ -43,6 +44,12 @@ of_pci_parse_bus_range(struct device_node *node, struct resource *res)
{
return -EINVAL;
}
+
+static inline int
+of_get_pci_domain_nr(struct device_node *node)
+{
+ return -1;
+}
#endif

#if defined(CONFIG_OF) && defined(CONFIG_PCI_MSI)
diff --git a/include/linux/pci.h b/include/linux/pci.h
index a494e5d..150da2d 100644
--- a/include/linux/pci.h
+++ b/include/linux/pci.h
@@ -1285,10 +1285,12 @@ void pci_cfg_access_unlock(struct pci_dev *dev);
*/
#ifdef CONFIG_PCI_DOMAINS
extern int pci_domains_supported;
+int pci_get_new_domain_nr(void);
#else
enum { pci_domains_supported = 0 };
static inline int pci_domain_nr(struct pci_bus *bus) { return 0; }
static inline int pci_proc_domain(struct pci_bus *bus) { return 0; }
+static inline int pci_get_new_domain_nr(void) { return -ENOSYS; }
#endif /* CONFIG_PCI_DOMAINS */

/*
@@ -1417,6 +1419,7 @@ static inline struct pci_dev *pci_get_bus_and_slot(unsigned int bus,

static inline int pci_domain_nr(struct pci_bus *bus) { return 0; }
static inline struct pci_dev *pci_dev_get(struct pci_dev *dev) { return NULL; }
+static inline int pci_get_new_domain_nr(void) { return -ENOSYS; }

#define dev_is_pci(d) (false)
#define dev_is_pf(d) (false)

[Liviu Dudau]

This is needed for calls into OF code that parses PCI ranges. It signals
support for memory mapped PCI I/O accesses that are described by device
trees.

Signed-off-by: Liviu Dudau <***@arm.com>
Signed-off-by: Bjorn Helgaas <***@google.com>
Reviewed-by: Catalin Marinas <***@arm.com>
Acked-by: Arnd Bergmann <***@arndb.de>
CC: Russell King <***@arm.linux.org.uk>
CC: Rob Herring <robh+***@kernel.org>
---
arch/arm/include/asm/io.h | 1 +
1 file changed, 1 insertion(+)

diff --git a/arch/arm/include/asm/io.h b/arch/arm/include/asm/io.h
index 3d23418..1805674 100644
--- a/arch/arm/include/asm/io.h
+++ b/arch/arm/include/asm/io.h
@@ -178,6 +178,7 @@ static inline void __iomem *__typesafe_io(unsigned long addr)

/* PCI fixed i/o mapping */
#define PCI_IO_VIRT_BASE 0xfee00000
+#define PCI_IOBASE ((void __iomem *)PCI_IO_VIRT_BASE)

#if defined(CONFIG_PCI)
void pci_ioremap_set_mem_type(int mem_type);

[Liviu Dudau]

Add pci_remap_iospace() to map bus I/O resources into the CPU virtual
address space. Architectures with special needs may provide their own
version, but most should be able to use this one.

This function is useful for PCI host bridge drivers that need to map the
PCI I/O resources into virtual memory space.

[bhelgaas: phys_addr description, drop temporary "err" variable]
Signed-off-by: Liviu Dudau <***@arm.com>
Signed-off-by: Bjorn Helgaas <***@google.com>
Reviewed-by: Rob Herring <***@kernel.org>
Reviewed-by: Catalin Marinas <***@arm.com>
CC: Arnd Bergmann <***@arndb.de>
---
drivers/pci/pci.c | 31 +++++++++++++++++++++++++++++++
include/asm-generic/pgtable.h | 4 ++++
include/linux/pci.h | 3 +++
3 files changed, 38 insertions(+)

diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c
index d36f35f..6e994fc 100644
--- a/drivers/pci/pci.c
+++ b/drivers/pci/pci.c
@@ -2704,6 +2704,37 @@ int pci_request_regions_exclusive(struct pci_dev *pdev, const char *res_name)
}
EXPORT_SYMBOL(pci_request_regions_exclusive);

+/**
+ * pci_remap_iospace - Remap the memory mapped I/O space
+ * @res: Resource describing the I/O space
+ * @phys_addr: physical address of range to be mapped
+ *
+ * Remap the memory mapped I/O space described by the @res
+ * and the CPU physical address @phys_addr into virtual address space.
+ * Only architectures that have memory mapped IO functions defined
+ * (and the PCI_IOBASE value defined) should call this function.
+ */
+int __weak pci_remap_iospace(const struct resource *res, phys_addr_t phys_addr)
+{
+#if defined(PCI_IOBASE) && defined(CONFIG_MMU)
+ unsigned long vaddr = (unsigned long)PCI_IOBASE + res->start;
+
+ if (!(res->flags & IORESOURCE_IO))
+ return -EINVAL;
+
+ if (res->end > IO_SPACE_LIMIT)
+ return -EINVAL;
+
+ return ioremap_page_range(vaddr, vaddr + resource_size(res), phys_addr,
+ pgprot_device(PAGE_KERNEL));
+#else
+ /* this architecture does not have memory mapped I/O space,
+ so this function should never be called */
+ WARN_ONCE(1, "This architecture does not support memory mapped I/O\n");
+ return -ENODEV;
+#endif
+}
+
static void __pci_set_master(struct pci_dev *dev, bool enable)
{
u16 old_cmd, cmd;
diff --git a/include/asm-generic/pgtable.h b/include/asm-generic/pgtable.h
index 53b2acc..977e545 100644
--- a/include/asm-generic/pgtable.h
+++ b/include/asm-generic/pgtable.h
@@ -249,6 +249,10 @@ static inline int pmd_same(pmd_t pmd_a, pmd_t pmd_b)
#define pgprot_writecombine pgprot_noncached
#endif

+#ifndef pgprot_device
+#define pgprot_device pgprot_noncached
+#endif
+
/*
* When walking page tables, get the address of the next boundary,
* or the end address of the range if that comes earlier. Although no
diff --git a/include/linux/pci.h b/include/linux/pci.h
index 150da2d..b4995fd 100644
--- a/include/linux/pci.h
+++ b/include/linux/pci.h
@@ -1100,6 +1100,9 @@ int __must_check pci_bus_alloc_resource(struct pci_bus *bus,
resource_size_t),
void *alignf_data);

+
+int pci_remap_iospace(const struct resource *res, phys_addr_t phys_addr);
+
static inline dma_addr_t pci_bus_address(struct pci_dev *pdev, int bar)
{
struct pci_bus_region region;

[Liviu Dudau]

The ranges property for a host bridge controller in DT describes the
mapping between the PCI bus address and the CPU physical address. The
resources framework however expects that the IO resources start at a pseudo
"port" address 0 (zero) and have a maximum size of IO_SPACE_LIMIT. The
conversion from PCI ranges to resources failed to take that into account,
returning a CPU physical address instead of a port number.

Also fix all the drivers that depend on the old behaviour by fetching the
CPU physical address based on the port number where it is being needed.

Signed-off-by: Liviu Dudau <***@arm.com>
Signed-off-by: Bjorn Helgaas <***@google.com>
Acked-by: Linus Walleij <***@linaro.org>
CC: Grant Likely <***@linaro.org>
CC: Rob Herring <robh+***@kernel.org>
CC: Arnd Bergmann <***@arndb.de>
CC: Thierry Reding <***@gmail.com>
CC: Simon Horman <***@verge.net.au>
CC: Catalin Marinas <***@arm.com>
---
arch/arm/mach-integrator/pci_v3.c | 23 ++++++++++----------
drivers/of/address.c | 44 +++++++++++++++++++++++++++++++++++----
drivers/pci/host/pci-tegra.c | 10 ++++++---
drivers/pci/host/pcie-rcar.c | 21 +++++++++++++------
include/linux/of_address.h | 6 +++---
5 files changed, 77 insertions(+), 27 deletions(-)

diff --git a/arch/arm/mach-integrator/pci_v3.c b/arch/arm/mach-integrator/pci_v3.c
index 05e1f73..c186a17 100644
--- a/arch/arm/mach-integrator/pci_v3.c
+++ b/arch/arm/mach-integrator/pci_v3.c
@@ -660,6 +660,7 @@ static void __init pci_v3_preinit(void)
{
unsigned long flags;
unsigned int temp;
+ phys_addr_t io_address = pci_pio_to_address(io_mem.start);

pcibios_min_mem = 0x00100000;

@@ -701,7 +702,7 @@ static void __init pci_v3_preinit(void)
/*
* Setup window 2 - PCI IO
*/
- v3_writel(V3_LB_BASE2, v3_addr_to_lb_base2(io_mem.start) |
+ v3_writel(V3_LB_BASE2, v3_addr_to_lb_base2(io_address) |
V3_LB_BASE_ENABLE);
v3_writew(V3_LB_MAP2, v3_addr_to_lb_map2(0));

@@ -742,6 +743,7 @@ static void __init pci_v3_preinit(void)
static void __init pci_v3_postinit(void)
{
unsigned int pci_cmd;
+ phys_addr_t io_address = pci_pio_to_address(io_mem.start);

pci_cmd = PCI_COMMAND_MEMORY |
PCI_COMMAND_MASTER | PCI_COMMAND_INVALIDATE;
@@ -758,7 +760,7 @@ static void __init pci_v3_postinit(void)
"interrupt: %d\n", ret);
#endif

- register_isa_ports(non_mem.start, io_mem.start, 0);
+ register_isa_ports(non_mem.start, io_address, 0);
}

/*
@@ -867,33 +869,32 @@ static int __init pci_v3_probe(struct platform_device *pdev)

for_each_of_pci_range(&parser, &range) {
if (!range.flags) {
- of_pci_range_to_resource(&range, np, &conf_mem);
+ ret = of_pci_range_to_resource(&range, np, &conf_mem);
conf_mem.name = "PCIv3 config";
}
if (range.flags & IORESOURCE_IO) {
- of_pci_range_to_resource(&range, np, &io_mem);
+ ret = of_pci_range_to_resource(&range, np, &io_mem);
io_mem.name = "PCIv3 I/O";
}
if ((range.flags & IORESOURCE_MEM) &&
!(range.flags & IORESOURCE_PREFETCH)) {
non_mem_pci = range.pci_addr;
non_mem_pci_sz = range.size;
- of_pci_range_to_resource(&range, np, &non_mem);
+ ret = of_pci_range_to_resource(&range, np, &non_mem);
non_mem.name = "PCIv3 non-prefetched mem";
}
if ((range.flags & IORESOURCE_MEM) &&
(range.flags & IORESOURCE_PREFETCH)) {
pre_mem_pci = range.pci_addr;
pre_mem_pci_sz = range.size;
- of_pci_range_to_resource(&range, np, &pre_mem);
+ ret = of_pci_range_to_resource(&range, np, &pre_mem);
pre_mem.name = "PCIv3 prefetched mem";
}
- }

- if (!conf_mem.start || !io_mem.start ||
- !non_mem.start || !pre_mem.start) {
- dev_err(&pdev->dev, "missing ranges in device node\n");
- return -EINVAL;
+ if (ret < 0) {
+ dev_err(&pdev->dev, "missing ranges in device node\n");
+ return ret;
+ }
}

pci_v3.map_irq = of_irq_parse_and_map_pci;
diff --git a/drivers/of/address.c b/drivers/of/address.c
index 327a574..afdb782 100644
--- a/drivers/of/address.c
+++ b/drivers/of/address.c
@@ -295,14 +295,50 @@ struct of_pci_range *of_pci_range_parser_one(struct of_pci_range_parser *parser,
}
EXPORT_SYMBOL_GPL(of_pci_range_parser_one);

-void of_pci_range_to_resource(struct of_pci_range *range,
- struct device_node *np, struct resource *res)
+/*
+ * of_pci_range_to_resource - Create a resource from an of_pci_range
+ * @range: the PCI range that describes the resource
+ * @np: device node where the range belongs to
+ * @res: pointer to a valid resource that will be updated to
+ * reflect the values contained in the range.
+ *
+ * Returns EINVAL if the range cannot be converted to resource.
+ *
+ * Note that if the range is an IO range, the resource will be converted
+ * using pci_address_to_pio() which can fail if it is called too early or
+ * if the range cannot be matched to any host bridge IO space (our case here).
+ * To guard against that we try to register the IO range first.
+ * If that fails we know that pci_address_to_pio() will do too.
+ */
+int of_pci_range_to_resource(struct of_pci_range *range,
+ struct device_node *np, struct resource *res)
{
+ int err;
res->flags = range->flags;
- res->start = range->cpu_addr;
- res->end = range->cpu_addr + range->size - 1;
res->parent = res->child = res->sibling = NULL;
res->name = np->full_name;
+
+ if (res->flags & IORESOURCE_IO) {
+ unsigned long port;
+ err = pci_register_io_range(range->cpu_addr, range->size);
+ if (err)
+ goto invalid_range;
+ port = pci_address_to_pio(range->cpu_addr);
+ if (port == (unsigned long)-1) {
+ err = -EINVAL;
+ goto invalid_range;
+ }
+ res->start = port;
+ } else {
+ res->start = range->cpu_addr;
+ }
+ res->end = res->start + range->size - 1;
+ return 0;
+
+invalid_range:
+ res->start = (resource_size_t)OF_BAD_ADDR;
+ res->end = (resource_size_t)OF_BAD_ADDR;
+ return err;
}
#endif /* CONFIG_PCI */

diff --git a/drivers/pci/host/pci-tegra.c b/drivers/pci/host/pci-tegra.c
index 0fb0fdb..946935d 100644
--- a/drivers/pci/host/pci-tegra.c
+++ b/drivers/pci/host/pci-tegra.c
@@ -626,13 +626,14 @@ DECLARE_PCI_FIXUP_FINAL(PCI_ANY_ID, PCI_ANY_ID, tegra_pcie_relax_enable);
static int tegra_pcie_setup(int nr, struct pci_sys_data *sys)
{
struct tegra_pcie *pcie = sys_to_pcie(sys);
+ phys_addr_t io_start = pci_pio_to_address(pcie->io.start);

pci_add_resource_offset(&sys->resources, &pcie->mem, sys->mem_offset);
pci_add_resource_offset(&sys->resources, &pcie->prefetch,
sys->mem_offset);
pci_add_resource(&sys->resources, &pcie->busn);

- pci_ioremap_io(nr * SZ_64K, pcie->io.start);
+ pci_ioremap_io(nr * SZ_64K, io_start);

return 1;
}
@@ -737,6 +738,7 @@ static irqreturn_t tegra_pcie_isr(int irq, void *arg)
static void tegra_pcie_setup_translations(struct tegra_pcie *pcie)
{
u32 fpci_bar, size, axi_address;
+ phys_addr_t io_start = pci_pio_to_address(pcie->io.start);

/* Bar 0: type 1 extended configuration space */
fpci_bar = 0xfe100000;
@@ -749,7 +751,7 @@ static void tegra_pcie_setup_translations(struct tegra_pcie *pcie)
/* Bar 1: downstream IO bar */
fpci_bar = 0xfdfc0000;
size = resource_size(&pcie->io);
- axi_address = pcie->io.start;
+ axi_address = io_start;
afi_writel(pcie, axi_address, AFI_AXI_BAR1_START);
afi_writel(pcie, size >> 12, AFI_AXI_BAR1_SZ);
afi_writel(pcie, fpci_bar, AFI_FPCI_BAR1);
@@ -1520,7 +1522,9 @@ static int tegra_pcie_parse_dt(struct tegra_pcie *pcie)
}

for_each_of_pci_range(&parser, &range) {
- of_pci_range_to_resource(&range, np, &res);
+ err = of_pci_range_to_resource(&range, np, &res);
+ if (err < 0)
+ return err;

switch (res.flags & IORESOURCE_TYPE_BITS) {
case IORESOURCE_IO:
diff --git a/drivers/pci/host/pcie-rcar.c b/drivers/pci/host/pcie-rcar.c
index 4884ee5..61158e0 100644
--- a/drivers/pci/host/pcie-rcar.c
+++ b/drivers/pci/host/pcie-rcar.c
@@ -323,6 +323,7 @@ static void rcar_pcie_setup_window(int win, struct rcar_pcie *pcie)

/* Setup PCIe address space mappings for each resource */
resource_size_t size;
+ resource_size_t res_start;
u32 mask;

rcar_pci_write_reg(pcie, 0x00000000, PCIEPTCTLR(win));
@@ -335,8 +336,13 @@ static void rcar_pcie_setup_window(int win, struct rcar_pcie *pcie)
mask = (roundup_pow_of_two(size) / SZ_128) - 1;
rcar_pci_write_reg(pcie, mask << 7, PCIEPAMR(win));

- rcar_pci_write_reg(pcie, upper_32_bits(res->start), PCIEPARH(win));
- rcar_pci_write_reg(pcie, lower_32_bits(res->start), PCIEPARL(win));
+ if (res->flags & IORESOURCE_IO)
+ res_start = pci_pio_to_address(res->start);
+ else
+ res_start = res->start;
+
+ rcar_pci_write_reg(pcie, upper_32_bits(res_start), PCIEPARH(win));
+ rcar_pci_write_reg(pcie, lower_32_bits(res_start), PCIEPARL(win));

/* First resource is for IO */
mask = PAR_ENABLE;
@@ -363,9 +369,10 @@ static int rcar_pcie_setup(int nr, struct pci_sys_data *sys)

rcar_pcie_setup_window(i, pcie);

- if (res->flags & IORESOURCE_IO)
- pci_ioremap_io(nr * SZ_64K, res->start);
- else
+ if (res->flags & IORESOURCE_IO) {
+ phys_addr_t io_start = pci_pio_to_address(res->start);
+ pci_ioremap_io(nr * SZ_64K, io_start);
+ } else
pci_add_resource(&sys->resources, res);
}
pci_add_resource(&sys->resources, &pcie->busn);
@@ -935,8 +942,10 @@ static int rcar_pcie_probe(struct platform_device *pdev)
}

for_each_of_pci_range(&parser, &range) {
- of_pci_range_to_resource(&range, pdev->dev.of_node,
+ err = of_pci_range_to_resource(&range, pdev->dev.of_node,
&pcie->res[win++]);
+ if (err < 0)
+ return err;

if (win > RCAR_PCI_MAX_RESOURCES)
break;
diff --git a/include/linux/of_address.h b/include/linux/of_address.h
index fa20aa1..7ebb877 100644
--- a/include/linux/of_address.h
+++ b/include/linux/of_address.h
@@ -129,9 +129,9 @@ extern const __be32 *of_get_pci_address(struct device_node *dev, int bar_no,
u64 *size, unsigned int *flags);
extern int of_pci_address_to_resource(struct device_node *dev, int bar,
struct resource *r);
-extern void of_pci_range_to_resource(struct of_pci_range *range,
- struct device_node *np,
- struct resource *res);
+extern int of_pci_range_to_resource(struct of_pci_range *range,
+ struct device_node *np,
+ struct resource *res);
#else /* CONFIG_OF_ADDRESS && CONFIG_PCI */
static inline int of_pci_address_to_resource(struct device_node *dev, int bar,
struct resource *r)

[Liviu Dudau]

Provide a function to parse the PCI DT ranges that can be used to create a
pci_host_bridge structure together with its associated bus.

Signed-off-by: Liviu Dudau <***@arm.com>
[make io_base parameter optional]
Signed-off-by: Robert Richter <***@cavium.com>
Signed-off-by: Bjorn Helgaas <***@google.com>
CC: Arnd Bergmann <***@arndb.de>
CC: Grant Likely <***@linaro.org>
CC: Rob Herring <robh+***@kernel.org>
CC: Catalin Marinas <***@arm.com>
---
drivers/of/of_pci.c | 117 +++++++++++++++++++++++++++++++++++++++++++++++++
include/linux/of_pci.h | 6 +++
2 files changed, 123 insertions(+)

diff --git a/drivers/of/of_pci.c b/drivers/of/of_pci.c
index 82d172f..8882b46 100644
--- a/drivers/of/of_pci.c
+++ b/drivers/of/of_pci.c
@@ -1,7 +1,9 @@
#include <linux/kernel.h>
#include <linux/export.h>
#include <linux/of.h>
+#include <linux/of_address.h>
#include <linux/of_pci.h>
+#include <linux/slab.h>

static inline int __of_pci_pci_compare(struct device_node *node,
unsigned int data)
@@ -114,6 +116,121 @@ int of_get_pci_domain_nr(struct device_node *node)
}
EXPORT_SYMBOL_GPL(of_get_pci_domain_nr);

+#if defined(CONFIG_OF_ADDRESS)
+/**
+ * of_pci_get_host_bridge_resources - Parse PCI host bridge resources from DT
+ * @dev: device node of the host bridge having the range property
+ * @busno: bus number associated with the bridge root bus
+ * @bus_max: maximum number of buses for this bridge
+ * @resources: list where the range of resources will be added after DT parsing
+ * @io_base: pointer to a variable that will contain on return the physical
+ * address for the start of the I/O range. Can be NULL if the caller doesn't
+ * expect IO ranges to be present in the device tree.
+ *
+ * It is the caller's job to free the @resources list.
+ *
+ * This function will parse the "ranges" property of a PCI host bridge device
+ * node and setup the resource mapping based on its content. It is expected
+ * that the property conforms with the Power ePAPR document.
+ *
+ * It returns zero if the range parsing has been successful or a standard error
+ * value if it failed.
+ */
+int of_pci_get_host_bridge_resources(struct device_node *dev,
+ unsigned char busno, unsigned char bus_max,
+ struct list_head *resources, resource_size_t *io_base)
+{
+ struct resource *res;
+ struct resource *bus_range;
+ struct of_pci_range range;
+ struct of_pci_range_parser parser;
+ char range_type[4];
+ int err;
+
+ if (io_base)
+ *io_base = (resource_size_t)OF_BAD_ADDR;
+
+ bus_range = kzalloc(sizeof(*bus_range), GFP_KERNEL);
+ if (!bus_range)
+ return -ENOMEM;
+
+ pr_info("PCI host bridge %s ranges:\n", dev->full_name);
+
+ err = of_pci_parse_bus_range(dev, bus_range);
+ if (err) {
+ bus_range->start = busno;
+ bus_range->end = bus_max;
+ bus_range->flags = IORESOURCE_BUS;
+ pr_info(" No bus range found for %s, using %pR\n",
+ dev->full_name, bus_range);
+ } else {
+ if (bus_range->end > bus_range->start + bus_max)
+ bus_range->end = bus_range->start + bus_max;
+ }
+ pci_add_resource(resources, bus_range);
+
+ /* Check for ranges property */
+ err = of_pci_range_parser_init(&parser, dev);
+ if (err)
+ goto parse_failed;
+
+ pr_debug("Parsing ranges property...\n");
+ for_each_of_pci_range(&parser, &range) {
+ /* Read next ranges element */
+ if ((range.flags & IORESOURCE_TYPE_BITS) == IORESOURCE_IO)
+ snprintf(range_type, 4, " IO");
+ else if ((range.flags & IORESOURCE_TYPE_BITS) == IORESOURCE_MEM)
+ snprintf(range_type, 4, "MEM");
+ else
+ snprintf(range_type, 4, "err");
+ pr_info(" %s %#010llx..%#010llx -> %#010llx\n", range_type,
+ range.cpu_addr, range.cpu_addr + range.size - 1,
+ range.pci_addr);
+
+ /*
+ * If we failed translation or got a zero-sized region
+ * then skip this range
+ */
+ if (range.cpu_addr == OF_BAD_ADDR || range.size == 0)
+ continue;
+
+ res = kzalloc(sizeof(struct resource), GFP_KERNEL);
+ if (!res) {
+ err = -ENOMEM;
+ goto parse_failed;
+ }
+
+ err = of_pci_range_to_resource(&range, dev, res);
+ if (err)
+ goto conversion_failed;
+
+ if (resource_type(res) == IORESOURCE_IO) {
+ if (!io_base) {
+ pr_err("I/O range found for %s. Please provide an io_base pointer to save CPU base address\n",
+ dev->full_name);
+ err = -EINVAL;
+ goto conversion_failed;
+ }
+ if (*io_base != (resource_size_t)OF_BAD_ADDR)
+ pr_warn("More than one I/O resource converted for %s. CPU base address for old range lost!\n",
+ dev->full_name);
+ *io_base = range.cpu_addr;
+ }
+
+ pci_add_resource_offset(resources, res, res->start - range.pci_addr);
+ }
+
+ return 0;
+
+conversion_failed:
+ kfree(res);
+parse_failed:
+ pci_free_resource_list(resources);
+ return err;
+}
+EXPORT_SYMBOL_GPL(of_pci_get_host_bridge_resources);
+#endif /* CONFIG_OF_ADDRESS */
+
#ifdef CONFIG_PCI_MSI

static LIST_HEAD(of_pci_msi_chip_list);
diff --git a/include/linux/of_pci.h b/include/linux/of_pci.h
index 71062e9..1fd207e 100644
--- a/include/linux/of_pci.h
+++ b/include/linux/of_pci.h
@@ -52,6 +52,12 @@ of_get_pci_domain_nr(struct device_node *node)
}
#endif

+#if defined(CONFIG_OF_ADDRESS)
+int of_pci_get_host_bridge_resources(struct device_node *dev,
+ unsigned char busno, unsigned char bus_max,
+ struct list_head *resources, resource_size_t *io_base);
+#endif
+
#if defined(CONFIG_OF) && defined(CONFIG_PCI_MSI)
int of_pci_msi_chip_add(struct msi_chip *chip);
void of_pci_msi_chip_remove(struct msi_chip *chip);

[Liviu Dudau]

The !CONFIG_GENERIC_IOMAP version of ioport_map() is wrong. It returns a
mapped, i.e., virtual, address that can start from zero and completely
ignores the PCI_IOBASE and IO_SPACE_LIMIT that most architectures that use
!CONFIG_GENERIC_MAP define.

Tested-by: Tanmay Inamdar <***@apm.com>
Signed-off-by: Liviu Dudau <***@arm.com>
Signed-off-by: Bjorn Helgaas <***@google.com>
Reviewed-by: Catalin Marinas <***@arm.com>
Acked-by: Arnd Bergmann <***@arndb.de>
---
include/asm-generic/io.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/include/asm-generic/io.h b/include/asm-generic/io.h
index 975e1cc..b8fdc57 100644
--- a/include/asm-generic/io.h
+++ b/include/asm-generic/io.h
@@ -331,7 +331,7 @@ static inline void iounmap(void __iomem *addr)
#ifndef CONFIG_GENERIC_IOMAP
static inline void __iomem *ioport_map(unsigned long port, unsigned int nr)
{
- return (void __iomem *) port;
+ return PCI_IOBASE + (port & IO_SPACE_LIMIT);
}

static inline void ioport_unmap(void __iomem *p)

[Liviu Dudau]

We need to enhance of_pci_range_to_resources() enough that it won't make
sense for it to be inline anymore. Move it to drivers/of/address.c,
keeping it under #ifdef CONFIG_PCI.

[bhelgaas: drop extra detail from changelog, move def under CONFIG_PCI]
Signed-off-by: Liviu Dudau <***@arm.com>
Signed-off-by: Bjorn Helgaas <***@google.com>
CC: Grant Likely <***@linaro.org>
CC: Rob Herring <robh+***@kernel.org>
CC: Arnd Bergmann <***@arndb.de>
CC: Catalin Marinas <***@arm.com>
---
drivers/of/address.c | 9 +++++++++
include/linux/of_address.h | 15 +++------------
2 files changed, 12 insertions(+), 12 deletions(-)

diff --git a/drivers/of/address.c b/drivers/of/address.c
index 758d4f0..327a574 100644
--- a/drivers/of/address.c
+++ b/drivers/of/address.c
@@ -295,6 +295,15 @@ struct of_pci_range *of_pci_range_parser_one(struct of_pci_range_parser *parser,
}
EXPORT_SYMBOL_GPL(of_pci_range_parser_one);

+void of_pci_range_to_resource(struct of_pci_range *range,
+ struct device_node *np, struct resource *res)
+{
+ res->flags = range->flags;
+ res->start = range->cpu_addr;
+ res->end = range->cpu_addr + range->size - 1;
+ res->parent = res->child = res->sibling = NULL;
+ res->name = np->full_name;
+}
#endif /* CONFIG_PCI */

/*
diff --git a/include/linux/of_address.h b/include/linux/of_address.h
index ecf913c..fa20aa1 100644
--- a/include/linux/of_address.h
+++ b/include/linux/of_address.h
@@ -129,18 +129,9 @@ extern const __be32 *of_get_pci_address(struct device_node *dev, int bar_no,
u64 *size, unsigned int *flags);
extern int of_pci_address_to_resource(struct device_node *dev, int bar,
struct resource *r);
-
-static inline void of_pci_range_to_resource(struct of_pci_range *range,
- struct device_node *np,
- struct resource *res)
-{
- res->flags = range->flags;
- res->start = range->cpu_addr;
- res->end = range->cpu_addr + range->size - 1;
- res->parent = res->child = res->sibling = NULL;
- res->name = np->full_name;
-}
-
+extern void of_pci_range_to_resource(struct of_pci_range *range,
+ struct device_node *np,
+ struct resource *res);
#else /* CONFIG_OF_ADDRESS && CONFIG_PCI */
static inline int of_pci_address_to_resource(struct device_node *dev, int bar,
struct resource *r)

[Liviu Dudau]

Some architectures do not have a simple view of the PCI I/O space and
instead use a range of CPU addresses that map to bus addresses. For some
architectures these ranges will be expressed by OF bindings in a device
tree file.

This patch introduces a pci_register_io_range() helper function with a
generic implementation that can be used by such architectures to keep track
of the I/O ranges described by the PCI bindings. If the PCI_IOBASE macro
is not defined, that signals lack of support for PCI and we return an
error.

In order to retrieve the CPU address associated with an I/O port, a new
helper function pci_pio_to_address() is introduced. This will search in
the list of ranges registered with pci_register_io_range() and return the
CPU address that corresponds to the given port.

Signed-off-by: Liviu Dudau <***@arm.com>
Signed-off-by: Bjorn Helgaas <***@google.com>
Reviewed-by: Catalin Marinas <***@arm.com>
Acked-by: Rob Herring <***@kernel.org>
CC: Grant Likely <***@linaro.org>
CC: Arnd Bergmann <***@arndb.de>
---
drivers/of/address.c | 109 +++++++++++++++++++++++++++++++++++++++++++++
include/linux/of_address.h | 2 +
2 files changed, 111 insertions(+)

diff --git a/drivers/of/address.c b/drivers/of/address.c
index e371825..758d4f0 100644
--- a/drivers/of/address.c
+++ b/drivers/of/address.c
@@ -5,6 +5,8 @@
#include <linux/module.h>
#include <linux/of_address.h>
#include <linux/pci_regs.h>
+#include <linux/sizes.h>
+#include <linux/slab.h>
#include <linux/string.h>

/* Max address size we deal with */
@@ -601,12 +603,119 @@ const __be32 *of_get_address(struct device_node *dev, int index, u64 *size,
}
EXPORT_SYMBOL(of_get_address);

+#ifdef PCI_IOBASE
+struct io_range {
+ struct list_head list;
+ phys_addr_t start;
+ resource_size_t size;
+};
+
+static LIST_HEAD(io_range_list);
+static DEFINE_SPINLOCK(io_range_lock);
+#endif
+
+/*
+ * Record the PCI IO range (expressed as CPU physical address + size).
+ * Return a negative value if an error has occured, zero otherwise
+ */
+int __weak pci_register_io_range(phys_addr_t addr, resource_size_t size)
+{
+ int err = 0;
+
+#ifdef PCI_IOBASE
+ struct io_range *range;
+ resource_size_t allocated_size = 0;
+
+ /* check if the range hasn't been previously recorded */
+ spin_lock(&io_range_lock);
+ list_for_each_entry(range, &io_range_list, list) {
+ if (addr >= range->start && addr + size <= range->start + size) {
+ /* range already registered, bail out */
+ goto end_register;
+ }
+ allocated_size += range->size;
+ }
+
+ /* range not registed yet, check for available space */
+ if (allocated_size + size - 1 > IO_SPACE_LIMIT) {
+ /* if it's too big check if 64K space can be reserved */
+ if (allocated_size + SZ_64K - 1 > IO_SPACE_LIMIT) {
+ err = -E2BIG;
+ goto end_register;
+ }
+
+ size = SZ_64K;
+ pr_warn("Requested IO range too big, new size set to 64K\n");
+ }
+
+ /* add the range to the list */
+ range = kzalloc(sizeof(*range), GFP_KERNEL);
+ if (!range) {
+ err = -ENOMEM;
+ goto end_register;
+ }
+
+ range->start = addr;
+ range->size = size;
+
+ list_add_tail(&range->list, &io_range_list);
+
+end_register:
+ spin_unlock(&io_range_lock);
+#endif
+
+ return err;
+}
+
+phys_addr_t pci_pio_to_address(unsigned long pio)
+{
+ phys_addr_t address = (phys_addr_t)OF_BAD_ADDR;
+
+#ifdef PCI_IOBASE
+ struct io_range *range;
+ resource_size_t allocated_size = 0;
+
+ if (pio > IO_SPACE_LIMIT)
+ return address;
+
+ spin_lock(&io_range_lock);
+ list_for_each_entry(range, &io_range_list, list) {
+ if (pio >= allocated_size && pio < allocated_size + range->size) {
+ address = range->start + pio - allocated_size;
+ break;
+ }
+ allocated_size += range->size;
+ }
+ spin_unlock(&io_range_lock);
+#endif
+
+ return address;
+}
+
unsigned long __weak pci_address_to_pio(phys_addr_t address)
{
+#ifdef PCI_IOBASE
+ struct io_range *res;
+ resource_size_t offset = 0;
+ unsigned long addr = -1;
+
+ spin_lock(&io_range_lock);
+ list_for_each_entry(res, &io_range_list, list) {
+ if (address >= res->start && address < res->start + res->size) {
+ addr = res->start - address + offset;
+ break;
+ }
+ offset += res->size;
+ }
+ spin_unlock(&io_range_lock);
+
+ return addr;
+#else
if (address > IO_SPACE_LIMIT)
return (unsigned long)-1;

return (unsigned long) address;
+#endif
}

static int __of_address_to_resource(struct device_node *dev,
diff --git a/include/linux/of_address.h b/include/linux/of_address.h
index fb7b722..f8cc7da 100644
--- a/include/linux/of_address.h
+++ b/include/linux/of_address.h
@@ -55,7 +55,9 @@ extern void __iomem *of_iomap(struct device_node *device, int index);
extern const __be32 *of_get_address(struct device_node *dev, int index,
u64 *size, unsigned int *flags);

+extern int pci_register_io_range(phys_addr_t addr, resource_size_t size);
extern unsigned long pci_address_to_pio(phys_addr_t addr);
+extern phys_addr_t pci_pio_to_address(unsigned long pio);

extern int of_pci_range_parser_init(struct of_pci_range_parser *parser,
struct device_node *node);

[Al Stone]

Post by Liviu Dudau
Some architectures do not have a simple view of the PCI I/O space and
instead use a range of CPU addresses that map to bus addresses. For some
architectures these ranges will be expressed by OF bindings in a device
tree file.
This patch introduces a pci_register_io_range() helper function with a
generic implementation that can be used by such architectures to keep track
of the I/O ranges described by the PCI bindings. If the PCI_IOBASE macro
is not defined, that signals lack of support for PCI and we return an
error.
In order to retrieve the CPU address associated with an I/O port, a new
helper function pci_pio_to_address() is introduced. This will search in
the list of ranges registered with pci_register_io_range() and return the
CPU address that corresponds to the given port.
---
drivers/of/address.c | 109 +++++++++++++++++++++++++++++++++++++++++++++
include/linux/of_address.h | 2 +
2 files changed, 111 insertions(+)
diff --git a/drivers/of/address.c b/drivers/of/address.c
index e371825..758d4f0 100644
--- a/drivers/of/address.c
+++ b/drivers/of/address.c
@@ -5,6 +5,8 @@
#include <linux/module.h>
#include <linux/of_address.h>
#include <linux/pci_regs.h>
+#include <linux/sizes.h>
+#include <linux/slab.h>
#include <linux/string.h>
/* Max address size we deal with */
@@ -601,12 +603,119 @@ const __be32 *of_get_address(struct device_node *dev, int index, u64 *size,
}
EXPORT_SYMBOL(of_get_address);
+#ifdef PCI_IOBASE
+struct io_range {
+ struct list_head list;
+ phys_addr_t start;
+ resource_size_t size;
+};
+
+static LIST_HEAD(io_range_list);
+static DEFINE_SPINLOCK(io_range_lock);
+#endif
+
+/*
+ * Record the PCI IO range (expressed as CPU physical address + size).
+ * Return a negative value if an error has occured, zero otherwise
+ */
+int __weak pci_register_io_range(phys_addr_t addr, resource_size_t size)
+{
+ int err = 0;
+
+#ifdef PCI_IOBASE
+ struct io_range *range;
+ resource_size_t allocated_size = 0;
+
+ /* check if the range hasn't been previously recorded */
+ spin_lock(&io_range_lock);
+ list_for_each_entry(range, &io_range_list, list) {
+ if (addr >= range->start && addr + size <= range->start + size) {
+ /* range already registered, bail out */
+ goto end_register;
+ }
+ allocated_size += range->size;
+ }
+
+ /* range not registed yet, check for available space */
+ if (allocated_size + size - 1 > IO_SPACE_LIMIT) {
+ /* if it's too big check if 64K space can be reserved */
+ if (allocated_size + SZ_64K - 1 > IO_SPACE_LIMIT) {
+ err = -E2BIG;
+ goto end_register;
+ }
+
+ size = SZ_64K;
+ pr_warn("Requested IO range too big, new size set to 64K\n");
+ }
+
+ /* add the range to the list */
+ range = kzalloc(sizeof(*range), GFP_KERNEL);
+ if (!range) {
+ err = -ENOMEM;
+ goto end_register;
+ }
+
+ range->start = addr;
+ range->size = size;
+
+ list_add_tail(&range->list, &io_range_list);
+
+ spin_unlock(&io_range_lock);
+#endif
+
+ return err;
+}
+
+phys_addr_t pci_pio_to_address(unsigned long pio)
+{
+ phys_addr_t address = (phys_addr_t)OF_BAD_ADDR;

This reference to OF_BAD_ADDR is the only thing I'm seeing in this
patch that is DT specific.

Couldn't these helper functions be more useful if provided outside
of DT, perhaps in the PCI code instead? I was giving some thought
to re-using them for ACPI support of PCI but don't want to have to
build DT if I'm not really going to use it.

Post by Liviu Dudau
+#ifdef PCI_IOBASE
+ struct io_range *range;
+ resource_size_t allocated_size = 0;
+
+ if (pio > IO_SPACE_LIMIT)
+ return address;
+
+ spin_lock(&io_range_lock);
+ list_for_each_entry(range, &io_range_list, list) {
+ if (pio >= allocated_size && pio < allocated_size + range->size) {
+ address = range->start + pio - allocated_size;
+ break;
+ }
+ allocated_size += range->size;
+ }
+ spin_unlock(&io_range_lock);
+#endif
+
+ return address;
+}
+
unsigned long __weak pci_address_to_pio(phys_addr_t address)
{
+#ifdef PCI_IOBASE
+ struct io_range *res;
+ resource_size_t offset = 0;
+ unsigned long addr = -1;
+
+ spin_lock(&io_range_lock);
+ list_for_each_entry(res, &io_range_list, list) {
+ if (address >= res->start && address < res->start + res->size) {
+ addr = res->start - address + offset;
+ break;
+ }
+ offset += res->size;
+ }
+ spin_unlock(&io_range_lock);
+
+ return addr;
+#else
if (address > IO_SPACE_LIMIT)
return (unsigned long)-1;
return (unsigned long) address;
+#endif
}
static int __of_address_to_resource(struct device_node *dev,
diff --git a/include/linux/of_address.h b/include/linux/of_address.h
index fb7b722..f8cc7da 100644
--- a/include/linux/of_address.h
+++ b/include/linux/of_address.h
@@ -55,7 +55,9 @@ extern void __iomem *of_iomap(struct device_node *device, int index);
extern const __be32 *of_get_address(struct device_node *dev, int index,
u64 *size, unsigned int *flags);
+extern int pci_register_io_range(phys_addr_t addr, resource_size_t size);
extern unsigned long pci_address_to_pio(phys_addr_t addr);
+extern phys_addr_t pci_pio_to_address(unsigned long pio);
extern int of_pci_range_parser_init(struct of_pci_range_parser *parser,
struct device_node *node);

[Liviu Dudau]

Post by Al Stone

Some architectures do not have a simple view of the PCI I/O space a=

nd

Post by Al Stone

instead use a range of CPU addresses that map to bus addresses. Fo=

r some

Post by Al Stone

architectures these ranges will be expressed by OF bindings in a de=

vice

Post by Al Stone

tree file.
=20
This patch introduces a pci_register_io_range() helper function wit=

h a

Post by Al Stone

generic implementation that can be used by such architectures to ke=

ep track

Post by Al Stone

of the I/O ranges described by the PCI bindings. If the PCI_IOBASE=

macro

Post by Al Stone

is not defined, that signals lack of support for PCI and we return =

an

Post by Al Stone

error.
=20
In order to retrieve the CPU address associated with an I/O port, a=

new

Post by Al Stone

helper function pci_pio_to_address() is introduced. This will sear=

ch in

Post by Al Stone

the list of ranges registered with pci_register_io_range() and retu=

rn the

Post by Al Stone

CPU address that corresponds to the given port.
=20
---
drivers/of/address.c | 109 +++++++++++++++++++++++++++++++++=

++++++++++++

Post by Al Stone

include/linux/of_address.h | 2 +
2 files changed, 111 insertions(+)
=20
diff --git a/drivers/of/address.c b/drivers/of/address.c
index e371825..758d4f0 100644
--- a/drivers/of/address.c
+++ b/drivers/of/address.c
@@ -5,6 +5,8 @@
#include <linux/module.h>
#include <linux/of_address.h>
#include <linux/pci_regs.h>
+#include <linux/sizes.h>
+#include <linux/slab.h>
#include <linux/string.h>
=20
/* Max address size we deal with */
@@ -601,12 +603,119 @@ const __be32 *of_get_address(struct device_n=

ode *dev, int index, u64 *size,

Post by Al Stone

}
EXPORT_SYMBOL(of_get_address);
=20
+#ifdef PCI_IOBASE
+struct io_range {
+ struct list_head list;
+ phys_addr_t start;
+ resource_size_t size;
+};
+
+static LIST_HEAD(io_range_list);
+static DEFINE_SPINLOCK(io_range_lock);
+#endif
+
+/*
+ * Record the PCI IO range (expressed as CPU physical address + si=

ze).

Post by Al Stone

+ * Return a negative value if an error has occured, zero otherwise
+ */
+int __weak pci_register_io_range(phys_addr_t addr, resource_size_t=

size)

Post by Al Stone

+{
+ int err =3D 0;
+
+#ifdef PCI_IOBASE
+ struct io_range *range;
+ resource_size_t allocated_size =3D 0;
+
+ /* check if the range hasn't been previously recorded */
+ spin_lock(&io_range_lock);
+ list_for_each_entry(range, &io_range_list, list) {
+ if (addr >=3D range->start && addr + size <=3D range->start + si=

ze) {

Post by Al Stone

+ /* range already registered, bail out */
+ goto end_register;
+ }
+ allocated_size +=3D range->size;
+ }
+
+ /* range not registed yet, check for available space */
+ if (allocated_size + size - 1 > IO_SPACE_LIMIT) {
+ /* if it's too big check if 64K space can be reserved */
+ if (allocated_size + SZ_64K - 1 > IO_SPACE_LIMIT) {
+ err =3D -E2BIG;
+ goto end_register;
+ }
+
+ size =3D SZ_64K;
+ pr_warn("Requested IO range too big, new size set to 64K\n");
+ }
+
+ /* add the range to the list */
+ range =3D kzalloc(sizeof(*range), GFP_KERNEL);
+ if (!range) {
+ err =3D -ENOMEM;
+ goto end_register;
+ }
+
+ range->start =3D addr;
+ range->size =3D size;
+
+ list_add_tail(&range->list, &io_range_list);
+
+ spin_unlock(&io_range_lock);
+#endif
+
+ return err;
+}
+
+phys_addr_t pci_pio_to_address(unsigned long pio)
+{
+ phys_addr_t address =3D (phys_addr_t)OF_BAD_ADDR;

Hi Al,

Post by Al Stone
=20
This reference to OF_BAD_ADDR is the only thing I'm seeing in this
patch that is DT specific.
=20
Couldn't these helper functions be more useful if provided outside
of DT, perhaps in the PCI code instead? I was giving some thought
to re-using them for ACPI support of PCI but don't want to have to
build DT if I'm not really going to use it.

The reason why I've put it (now) in drivers/of is that the code is only
used by DT specific code. At some moment one of the older series put
it into drivers/pci but I was trying to make it more clear that this
is DT specific.

If you find this useful for ACPI (and this series lands in v3.18) then
I suggest you send a patch to move it into drivers/pci?

Best regards,
Liviu

Post by Al Stone
=20

+#ifdef PCI_IOBASE
+ struct io_range *range;
+ resource_size_t allocated_size =3D 0;
+
+ if (pio > IO_SPACE_LIMIT)
+ return address;
+
+ spin_lock(&io_range_lock);
+ list_for_each_entry(range, &io_range_list, list) {
+ if (pio >=3D allocated_size && pio < allocated_size + range->siz=

e) {

Post by Al Stone

+ address =3D range->start + pio - allocated_size;
+ break;
+ }
+ allocated_size +=3D range->size;
+ }
+ spin_unlock(&io_range_lock);
+#endif
+
+ return address;
+}
+
unsigned long __weak pci_address_to_pio(phys_addr_t address)
{
+#ifdef PCI_IOBASE
+ struct io_range *res;
+ resource_size_t offset =3D 0;
+ unsigned long addr =3D -1;
+
+ spin_lock(&io_range_lock);
+ list_for_each_entry(res, &io_range_list, list) {
+ if (address >=3D res->start && address < res->start + res->size)=

{

Post by Al Stone

+ addr =3D res->start - address + offset;
+ break;
+ }
+ offset +=3D res->size;
+ }
+ spin_unlock(&io_range_lock);
+
+ return addr;
+#else
if (address > IO_SPACE_LIMIT)
return (unsigned long)-1;
=20
return (unsigned long) address;
+#endif
}
=20
static int __of_address_to_resource(struct device_node *dev,
diff --git a/include/linux/of_address.h b/include/linux/of_address.=

h

Post by Al Stone

index fb7b722..f8cc7da 100644
--- a/include/linux/of_address.h
+++ b/include/linux/of_address.h
@@ -55,7 +55,9 @@ extern void __iomem *of_iomap(struct device_node =

*device, int index);

Post by Al Stone

extern const __be32 *of_get_address(struct device_node *dev, int i=

ndex,

Post by Al Stone

u64 *size, unsigned int *flags);
=20
+extern int pci_register_io_range(phys_addr_t addr, resource_size_t=

size);

Post by Al Stone

extern unsigned long pci_address_to_pio(phys_addr_t addr);
+extern phys_addr_t pci_pio_to_address(unsigned long pio);
=20
extern int of_pci_range_parser_init(struct of_pci_range_parser *pa=

rser,

Post by Al Stone

struct device_node *node);
=20

=20
=20
--=20
ciao,
al
-----------------------------------
Al Stone
Software Engineer
Red Hat, Inc.
-----------------------------------
=20

--=20
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
| I would like to |
| fix the world, |
| but they're not |
| giving me the |
\ source code! /
---------------
=C2=AF\_(=E3=83=84)_/=C2=AF

[Liviu Dudau]

Use the generic PCI domain and OF functions to provide support for PCI
on arm64.

[bhelgaas: Change comments to use generic PCI, not just PCIe. Nothing at
this level is PCIe-specific.]
Signed-off-by: Liviu Dudau <***@arm.com>
Signed-off-by: Bjorn Helgaas <***@google.com>
Acked-by: Catalin Marinas <***@arm.com>
---
arch/arm64/Kconfig | 22 ++++++++++++-
arch/arm64/include/asm/Kbuild | 1 +
arch/arm64/include/asm/io.h | 3 +-
arch/arm64/include/asm/pci.h | 37 +++++++++++++++++++++
arch/arm64/include/asm/pgtable.h | 2 ++
arch/arm64/kernel/Makefile | 1 +
arch/arm64/kernel/pci.c | 70 ++++++++++++++++++++++++++++++++++++++++
7 files changed, 134 insertions(+), 2 deletions(-)
create mode 100644 arch/arm64/include/asm/pci.h
create mode 100644 arch/arm64/kernel/pci.c

diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig
index fd4e81a..bc97147 100644
--- a/arch/arm64/Kconfig
+++ b/arch/arm64/Kconfig
@@ -81,7 +81,7 @@ config MMU
def_bool y

config NO_IOPORT_MAP
- def_bool y
+ def_bool y if !PCI

config STACKTRACE_SUPPORT
def_bool y
@@ -156,6 +156,26 @@ menu "Bus support"
config ARM_AMBA
bool

+config PCI
+ bool "PCI support"
+ help
+ This feature enables support for PCI bus system. If you say Y
+ here, the kernel will include drivers and infrastructure code
+ to support PCI bus devices.
+
+config PCI_DOMAINS
+ def_bool PCI
+
+config PCI_DOMAINS_GENERIC
+ def_bool PCI
+
+config PCI_SYSCALL
+ def_bool PCI
+
+source "drivers/pci/Kconfig"
+source "drivers/pci/pcie/Kconfig"
+source "drivers/pci/hotplug/Kconfig"
+
endmenu

menu "Kernel Features"
diff --git a/arch/arm64/include/asm/Kbuild b/arch/arm64/include/asm/Kbuild
index 0b3fcf8..07cb417 100644
--- a/arch/arm64/include/asm/Kbuild
+++ b/arch/arm64/include/asm/Kbuild
@@ -29,6 +29,7 @@ generic-y += mman.h
generic-y += msgbuf.h
generic-y += mutex.h
generic-y += pci.h
+generic-y += pci-bridge.h
generic-y += poll.h
generic-y += preempt.h
generic-y += resource.h
diff --git a/arch/arm64/include/asm/io.h b/arch/arm64/include/asm/io.h
index e0ecdcf..f998d90 100644
--- a/arch/arm64/include/asm/io.h
+++ b/arch/arm64/include/asm/io.h
@@ -121,7 +121,8 @@ static inline u64 __raw_readq(const volatile void __iomem *addr)
/*
* I/O port access primitives.
*/
-#define IO_SPACE_LIMIT 0xffff
+#define arch_has_dev_port() (1)
+#define IO_SPACE_LIMIT (SZ_32M - 1)
#define PCI_IOBASE ((void __iomem *)(MODULES_VADDR - SZ_32M))

static inline u8 inb(unsigned long addr)
diff --git a/arch/arm64/include/asm/pci.h b/arch/arm64/include/asm/pci.h
new file mode 100644
index 0000000..872ba93
--- /dev/null
+++ b/arch/arm64/include/asm/pci.h
@@ -0,0 +1,37 @@
+#ifndef __ASM_PCI_H
+#define __ASM_PCI_H
+#ifdef __KERNEL__
+
+#include <linux/types.h>
+#include <linux/slab.h>
+#include <linux/dma-mapping.h>
+
+#include <asm/io.h>
+#include <asm-generic/pci-bridge.h>
+#include <asm-generic/pci-dma-compat.h>
+
+#define PCIBIOS_MIN_IO 0x1000
+#define PCIBIOS_MIN_MEM 0
+
+/*
+ * Set to 1 if the kernel should re-assign all PCI bus numbers
+ */
+#define pcibios_assign_all_busses() \
+ (pci_has_flag(PCI_REASSIGN_ALL_BUS))
+
+/*
+ * PCI address space differs from physical memory address space
+ */
+#define PCI_DMA_BUS_IS_PHYS (0)
+
+extern int isa_dma_bridge_buggy;
+
+#ifdef CONFIG_PCI
+static inline int pci_proc_domain(struct pci_bus *bus)
+{
+ return 1;
+}
+#endif /* CONFIG_PCI */
+
+#endif /* __KERNEL__ */
+#endif /* __ASM_PCI_H */
diff --git a/arch/arm64/include/asm/pgtable.h b/arch/arm64/include/asm/pgtable.h
index ffe1ba0..a968523 100644
--- a/arch/arm64/include/asm/pgtable.h
+++ b/arch/arm64/include/asm/pgtable.h
@@ -296,6 +296,8 @@ static inline int has_transparent_hugepage(void)
__pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_DEVICE_nGnRnE) | PTE_PXN | PTE_UXN)
#define pgprot_writecombine(prot) \
__pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_NORMAL_NC) | PTE_PXN | PTE_UXN)
+#define pgprot_device(prot) \
+ __pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_DEVICE_nGnRE) | PTE_PXN | PTE_UXN)
#define __HAVE_PHYS_MEM_ACCESS_PROT
struct file;
extern pgprot_t phys_mem_access_prot(struct file *file, unsigned long pfn,
diff --git a/arch/arm64/kernel/Makefile b/arch/arm64/kernel/Makefile
index df7ef87..1ed5a06 100644
--- a/arch/arm64/kernel/Makefile
+++ b/arch/arm64/kernel/Makefile
@@ -29,6 +29,7 @@ arm64-obj-$(CONFIG_ARM64_CPU_SUSPEND) += sleep.o suspend.o
arm64-obj-$(CONFIG_JUMP_LABEL) += jump_label.o
arm64-obj-$(CONFIG_KGDB) += kgdb.o
arm64-obj-$(CONFIG_EFI) += efi.o efi-stub.o efi-entry.o
+arm64-obj-$(CONFIG_PCI) += pci.o

obj-y += $(arm64-obj-y) vdso/
obj-m += $(arm64-obj-m)
diff --git a/arch/arm64/kernel/pci.c b/arch/arm64/kernel/pci.c
new file mode 100644
index 0000000..ce5836c
--- /dev/null
+++ b/arch/arm64/kernel/pci.c
@@ -0,0 +1,70 @@
+/*
+ * Code borrowed from powerpc/kernel/pci-common.c
+ *
+ * Copyright (C) 2003 Anton Blanchard <***@au.ibm.com>, IBM
+ * Copyright (C) 2014 ARM Ltd.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ */
+
+#include <linux/init.h>
+#include <linux/io.h>
+#include <linux/kernel.h>
+#include <linux/mm.h>
+#include <linux/of_pci.h>
+#include <linux/of_platform.h>
+#include <linux/slab.h>
+
+#include <asm/pci-bridge.h>
+
+/*
+ * Called after each bus is probed, but before its children are examined
+ */
+void pcibios_fixup_bus(struct pci_bus *bus)
+{
+ /* nothing to do, expected to be removed in the future */
+}
+
+/*
+ * We don't have to worry about legacy ISA devices, so nothing to do here
+ */
+resource_size_t pcibios_align_resource(void *data, const struct resource *res,
+ resource_size_t size, resource_size_t align)
+{
+ return res->start;
+}
+
+/*
+ * Try to assign the IRQ number from DT when adding a new device
+ */
+int pcibios_add_device(struct pci_dev *dev)
+{
+ dev->irq = of_irq_parse_and_map_pci(dev, 0, 0);
+
+ return 0;
+}
+
+
+#ifdef CONFIG_PCI_DOMAINS_GENERIC
+static bool dt_domain_found = false;
+
+void pci_bus_assign_domain_nr(struct pci_bus *bus, struct device *parent)
+{
+ int domain = of_get_pci_domain_nr(parent->of_node);
+
+ if (domain >= 0) {
+ dt_domain_found = true;
+ } else if (dt_domain_found == true) {
+ dev_err(parent, "Node %s is missing \"linux,pci-domain\" property in DT\n",
+ parent->of_node->full_name);
+ return;
+ } else {
+ domain = pci_get_new_domain_nr();
+ }
+
+ bus->domain_nr = domain;
+}
+#endif

[Liviu Dudau]

From: Bjorn Helgaas <***@google.com>

of_pci_range_to_resource() was previously defined always, but it's only
used by PCI code, so move the definition inside the CONFIG_OF_ADDRESS &&
CONFIG_PCI block.

Signed-off-by: Bjorn Helgaas <***@google.com>
---
include/linux/of_address.h | 24 ++++++++++++------------
1 file changed, 12 insertions(+), 12 deletions(-)

diff --git a/include/linux/of_address.h b/include/linux/of_address.h
index f8cc7da..ecf913c 100644
--- a/include/linux/of_address.h
+++ b/include/linux/of_address.h
@@ -23,17 +23,6 @@ struct of_pci_range {
#define for_each_of_pci_range(parser, range) \
for (; of_pci_range_parser_one(parser, range);)

-static inline void of_pci_range_to_resource(struct of_pci_range *range,
- struct device_node *np,
- struct resource *res)
-{
- res->flags = range->flags;
- res->start = range->cpu_addr;
- res->end = range->cpu_addr + range->size - 1;
- res->parent = res->child = res->sibling = NULL;
- res->name = np->full_name;
-}
-
/* Translate a DMA address from device space to CPU space */
extern u64 of_translate_dma_address(struct device_node *dev,
const __be32 *in_addr);
@@ -140,6 +129,18 @@ extern const __be32 *of_get_pci_address(struct device_node *dev, int bar_no,
u64 *size, unsigned int *flags);
extern int of_pci_address_to_resource(struct device_node *dev, int bar,
struct resource *r);
+
+static inline void of_pci_range_to_resource(struct of_pci_range *range,
+ struct device_node *np,
+ struct resource *res)
+{
+ res->flags = range->flags;
+ res->start = range->cpu_addr;
+ res->end = range->cpu_addr + range->size - 1;
+ res->parent = res->child = res->sibling = NULL;
+ res->name = np->full_name;
+}
+
#else /* CONFIG_OF_ADDRESS && CONFIG_PCI */
static inline int of_pci_address_to_resource(struct device_node *dev, int bar,
struct resource *r)
@@ -155,4 +156,3 @@ static inline const __be32 *of_get_pci_address(struct device_node *dev,
#endif /* CONFIG_OF_ADDRESS && CONFIG_PCI */

#endif /* __OF_ADDRESS_H */
-

[Bjorn Helgaas]

This is my version 13 of the attempt at adding support for generic PCI host
bridge controllers. It contains only cleanups to make it play nice with the
linux-next tree as of 09/25. If Bjorn deems it safe, now that it looks like
asm-generic is going to revert some of its more aggresive patches, he has the
choice of queueing it into linux-next again.
...

These patches above were already on my pci/host-generic branch and in
linux-next:

asm-generic/io.h: Fix ioport_map() for !CONFIG_GENERIC_IOMAP
of/pci: Add pci_register_io_range() and pci_pio_to_address()
ARM: Define PCI_IOBASE as the base of virtual PCI IO space
of/pci: Define of_pci_range_to_resource() only when CONFIG_PCI=y
of/pci: Move of_pci_range_to_resources() to of/address.c
of/pci: Fix the conversion of IO ranges into IO resources

I added these three patches to my pci/host-generic branch:

PCI: Add generic domain handling
of/pci: Add pci_get_new_domain_nr() and of_get_pci_domain_nr()
of/pci: Add support for parsing PCI host bridge resources from DT

Yinghai pointed out a problem with this one, so I omitted it:

PCI: Assign unassigned bus resources in pci_scan_root_bus()

I added this one to my pci/host-generic branch:

PCI: Add pci_remap_iospace() to map bus I/O resources

I assume this depends on the pci_scan_root_bus() change (if not, let me
know), so I omitted this one:

arm64: Add architectural support for PCI

Bjorn

[Liviu Dudau]

Post by Bjorn Helgaas

This is my version 13 of the attempt at adding support for generic =

PCI host

Post by Bjorn Helgaas

bridge controllers. It contains only cleanups to make it play nice =

with the

Post by Bjorn Helgaas

linux-next tree as of 09/25. If Bjorn deems it safe, now that it lo=

oks like

Post by Bjorn Helgaas

asm-generic is going to revert some of its more aggresive patches, =

he has the

Post by Bjorn Helgaas

choice of queueing it into linux-next again.
...

=20
These patches above were already on my pci/host-generic branch and in
=20
asm-generic/io.h: Fix ioport_map() for !CONFIG_GENERIC_IOMAP

This ^ ...

Post by Bjorn Helgaas
of/pci: Add pci_register_io_range() and pci_pio_to_address()
ARM: Define PCI_IOBASE as the base of virtual PCI IO space

and this ^ need to be refreshed from my series otherwise we will get co=
nflicts with
asm-generic branch (either now or in the future). While the asm-generic=
/io.h
cast is arguably superflous, we need to define PCI_IOBASE as a void __i=
omem* to
match all other standard declarations of PCI_IOBASE.

Post by Bjorn Helgaas
of/pci: Define of_pci_range_to_resource() only when CONFIG_PCI=3Dy
of/pci: Move of_pci_range_to_resources() to of/address.c
of/pci: Fix the conversion of IO ranges into IO resources
=20
=20
PCI: Add generic domain handling
of/pci: Add pci_get_new_domain_nr() and of_get_pci_domain_nr()
of/pci: Add support for parsing PCI host bridge resources from DT

I can see these patches added to pci/host-generic but not on pci/next.

Post by Bjorn Helgaas
=20
=20
PCI: Assign unassigned bus resources in pci_scan_root_bus()

Thats fine, host bridge drivers will have to work around pci_scan_root_=
bus() reduced
functionality for now.

Post by Bjorn Helgaas
=20
=20
PCI: Add pci_remap_iospace() to map bus I/O resources
=20
I assume this depends on the pci_scan_root_bus() change (if not, let =

me

Post by Bjorn Helgaas
=20
arm64: Add architectural support for PCI

No, there is no dependency there on pci_scan_root_bus(), it can go in t=
he series.
The only thing that depends on a feature rich pci_scan_root_bus() is th=
e host
bridge driver in order to be able to use only one line to process the r=
oot bus.

Thanks for huge support in getting these patches in and I do hope I'm n=
ot being
too much of a burden to you.

Best regards,
Liviu

Post by Bjorn Helgaas
=20
Bjorn
--
To unsubscribe from this list: send the line "unsubscribe linux-pci" =

in

Post by Bjorn Helgaas
More majordomo info at http://vger.kernel.org/majordomo-info.html
=20

--=20
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
| I would like to |
| fix the world, |
| but they're not |
| giving me the |
\ source code! /
---------------
=C2=AF\_(=E3=83=84)_/=C2=AF

[Bjorn Helgaas]

Post by Liviu Dudau

Post by Bjorn Helgaas

This is my version 13 of the attempt at adding support for generic PCI host
bridge controllers. It contains only cleanups to make it play nice with the
linux-next tree as of 09/25. If Bjorn deems it safe, now that it looks like
asm-generic is going to revert some of its more aggresive patches, he has the
choice of queueing it into linux-next again.
...

These patches above were already on my pci/host-generic branch and in
asm-generic/io.h: Fix ioport_map() for !CONFIG_GENERIC_IOMAP

This ^ ...

Post by Bjorn Helgaas
of/pci: Add pci_register_io_range() and pci_pio_to_address()
ARM: Define PCI_IOBASE as the base of virtual PCI IO space

and this ^ need to be refreshed from my series otherwise we will get conflicts with
asm-generic branch (either now or in the future). While the asm-generic/io.h
cast is arguably superflous, we need to define PCI_IOBASE as a void __iomem* to
match all other standard declarations of PCI_IOBASE.

Post by Bjorn Helgaas
of/pci: Define of_pci_range_to_resource() only when CONFIG_PCI=y
of/pci: Move of_pci_range_to_resources() to of/address.c
of/pci: Fix the conversion of IO ranges into IO resources
PCI: Add generic domain handling
of/pci: Add pci_get_new_domain_nr() and of_get_pci_domain_nr()
of/pci: Add support for parsing PCI host bridge resources from DT

I can see these patches added to pci/host-generic but not on pci/next.

Right. I leave things on topic branches for a day or two to give a chance
for Fengguang's auto-builder to find problems before I merge them into the
more public "next" or "for-linus" branches.

Post by Liviu Dudau

Post by Bjorn Helgaas
PCI: Assign unassigned bus resources in pci_scan_root_bus()

Thats fine, host bridge drivers will have to work around pci_scan_root_bus() reduced
functionality for now.

Well, it's not really "reduced functionality." It is unchanged by this
series and host bridge drivers can continue using it the same way they have
in the past. It's just that we'd like to make it smarter someday.

Post by Liviu Dudau

Post by Bjorn Helgaas
PCI: Add pci_remap_iospace() to map bus I/O resources
I assume this depends on the pci_scan_root_bus() change (if not, let me
arm64: Add architectural support for PCI

No, there is no dependency there on pci_scan_root_bus(), it can go in the series.
The only thing that depends on a feature rich pci_scan_root_bus() is the host
bridge driver in order to be able to use only one line to process the root bus.

OK, I rebuilt pci/host-generic from scratch. It consists of your v13
patches + Arnd's build fix for pci_pio_to_address() in !CONFIG_OF configs.

Bjorn
--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to majordomo-***@public.gmane.org
More majordomo info at http://vger.kernel.org/majordomo-info.html

[Liviu Dudau]

Post by Liviu Dudau

This is my version 13 of the attempt at adding support for gene=

ric PCI host

Post by Liviu Dudau

bridge controllers. It contains only cleanups to make it play n=

ice with the

Post by Liviu Dudau

linux-next tree as of 09/25. If Bjorn deems it safe, now that i=

t looks like

Post by Liviu Dudau

asm-generic is going to revert some of its more aggresive patch=

es, he has the

Post by Liviu Dudau

choice of queueing it into linux-next again.
...

=20
These patches above were already on my pci/host-generic branch an=

d in

Post by Liviu Dudau

=20
asm-generic/io.h: Fix ioport_map() for !CONFIG_GENERIC_IOMAP

This ^ ...
=20

of/pci: Add pci_register_io_range() and pci_pio_to_address()
ARM: Define PCI_IOBASE as the base of virtual PCI IO space

=20
and this ^ need to be refreshed from my series otherwise we will ge=

t conflicts with

Post by Liviu Dudau
asm-generic branch (either now or in the future). While the asm-gen=

eric/io.h

Post by Liviu Dudau
cast is arguably superflous, we need to define PCI_IOBASE as a void=

__iomem* to

Post by Liviu Dudau
match all other standard declarations of PCI_IOBASE.
=20

of/pci: Define of_pci_range_to_resource() only when CONFIG_PCI=

=3Dy

Post by Liviu Dudau

of/pci: Move of_pci_range_to_resources() to of/address.c
of/pci: Fix the conversion of IO ranges into IO resources
=20
=20
PCI: Add generic domain handling
of/pci: Add pci_get_new_domain_nr() and of_get_pci_domain_nr()
of/pci: Add support for parsing PCI host bridge resources from=

DT

Post by Liviu Dudau
=20
I can see these patches added to pci/host-generic but not on pci/ne=

xt.

=20
Right. I leave things on topic branches for a day or two to give a c=

hance

for Fengguang's auto-builder to find problems before I merge them int=

o the

more public "next" or "for-linus" branches.
=20

Post by Liviu Dudau

=20
PCI: Assign unassigned bus resources in pci_scan_root_bus()

=20
Thats fine, host bridge drivers will have to work around pci_scan_r=

oot_bus() reduced

Post by Liviu Dudau
functionality for now.

=20
Well, it's not really "reduced functionality." It is unchanged by th=

is

series and host bridge drivers can continue using it the same way the=

y have

in the past. It's just that we'd like to make it smarter someday.
=20

Post by Liviu Dudau

=20
PCI: Add pci_remap_iospace() to map bus I/O resources
=20
I assume this depends on the pci_scan_root_bus() change (if not, =

let me

Post by Liviu Dudau

=20
arm64: Add architectural support for PCI

=20
No, there is no dependency there on pci_scan_root_bus(), it can go =

in the series.

Post by Liviu Dudau
The only thing that depends on a feature rich pci_scan_root_bus() i=

s the host

Post by Liviu Dudau
bridge driver in order to be able to use only one line to process t=

he root bus.

=20
OK, I rebuilt pci/host-generic from scratch. It consists of your v13
patches + Arnd's build fix for pci_pio_to_address() in !CONFIG_OF con=

figs.

A big gesture of gratitude towards you!!

I'm hoping the rest of the preparations for v3.18 will go smoothly with=
out having
to take any more of your time.

Best regards,
Liviu

=20
Bjorn
=20

--=20
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
| I would like to |
| fix the world, |
| but they're not |
| giving me the |
\ source code! /
---------------
=C2=AF\_(=E3=83=84)_/=C2=AF

[Liviu Dudau]

Post by Liviu Dudau

This is my version 13 of the attempt at adding support for gene=

ric PCI host

Post by Liviu Dudau

bridge controllers. It contains only cleanups to make it play n=

ice with the

Post by Liviu Dudau

linux-next tree as of 09/25. If Bjorn deems it safe, now that i=

t looks like

Post by Liviu Dudau

asm-generic is going to revert some of its more aggresive patch=

es, he has the

Post by Liviu Dudau

choice of queueing it into linux-next again.
...

=20
These patches above were already on my pci/host-generic branch an=

d in

Post by Liviu Dudau

=20
asm-generic/io.h: Fix ioport_map() for !CONFIG_GENERIC_IOMAP

This ^ ...
=20

of/pci: Add pci_register_io_range() and pci_pio_to_address()
ARM: Define PCI_IOBASE as the base of virtual PCI IO space

=20
and this ^ need to be refreshed from my series otherwise we will ge=

t conflicts with

Post by Liviu Dudau
asm-generic branch (either now or in the future). While the asm-gen=

eric/io.h

Post by Liviu Dudau
cast is arguably superflous, we need to define PCI_IOBASE as a void=

__iomem* to

Post by Liviu Dudau
match all other standard declarations of PCI_IOBASE.
=20

of/pci: Define of_pci_range_to_resource() only when CONFIG_PCI=

=3Dy

Post by Liviu Dudau

of/pci: Move of_pci_range_to_resources() to of/address.c
of/pci: Fix the conversion of IO ranges into IO resources
=20
=20
PCI: Add generic domain handling
of/pci: Add pci_get_new_domain_nr() and of_get_pci_domain_nr()
of/pci: Add support for parsing PCI host bridge resources from=

DT

Post by Liviu Dudau
=20
I can see these patches added to pci/host-generic but not on pci/ne=

xt.

=20
Right. I leave things on topic branches for a day or two to give a c=

hance

for Fengguang's auto-builder to find problems before I merge them int=

o the

more public "next" or "for-linus" branches.
=20

Post by Liviu Dudau

=20
PCI: Assign unassigned bus resources in pci_scan_root_bus()

=20
Thats fine, host bridge drivers will have to work around pci_scan_r=

oot_bus() reduced

Post by Liviu Dudau
functionality for now.

=20
Well, it's not really "reduced functionality." It is unchanged by th=

is

series and host bridge drivers can continue using it the same way the=

y have

in the past. It's just that we'd like to make it smarter someday.
=20

Post by Liviu Dudau

=20
PCI: Add pci_remap_iospace() to map bus I/O resources
=20
I assume this depends on the pci_scan_root_bus() change (if not, =

let me

Post by Liviu Dudau

=20
arm64: Add architectural support for PCI

=20
No, there is no dependency there on pci_scan_root_bus(), it can go =

in the series.

Post by Liviu Dudau
The only thing that depends on a feature rich pci_scan_root_bus() i=

s the host

Post by Liviu Dudau
bridge driver in order to be able to use only one line to process t=

he root bus.

=20
OK, I rebuilt pci/host-generic from scratch. It consists of your v13
patches + Arnd's build fix for pci_pio_to_address() in !CONFIG_OF con=

figs.

Something went wrong with the integration, patch 02 adds another defini=
tion of=20
of_pci_range_to_resource() before it is moved out of the header file fo=
r some reason.

Best regards,
Liviu

=20
Bjorn
=20

--=20
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
| I would like to |
| fix the world, |
| but they're not |
| giving me the |
\ source code! /
---------------
=C2=AF\_(=E3=83=84)_/=C2=AF

[Robert Richter]

Liviu, Bjorn,

Post by Bjorn Helgaas
OK, I rebuilt pci/host-generic from scratch. It consists of your v13
patches + Arnd's build fix for pci_pio_to_address() in !CONFIG_OF configs.

Something went wrong with the integration, patch 02 adds another definition of
of_pci_range_to_resource() before it is moved out of the header file for some reason.

I assume pci/host-generic is the latest now with this issue fixed as
the commit date is 2014-10-01 past you message above, right? So is it
ok to rebase our host controller driver onto pci/host-generic or will
there be further updates or any other branch that is newer?

Thanks,

-Robert

[Liviu Dudau]

Post by Robert Richter
Liviu, Bjorn,
=20

OK, I rebuilt pci/host-generic from scratch. It consists of your=

v13

Post by Robert Richter

patches + Arnd's build fix for pci_pio_to_address() in !CONFIG_OF=

configs.

Post by Robert Richter

=20
Something went wrong with the integration, patch 02 adds another de=

finition of=20

Post by Robert Richter

of_pci_range_to_resource() before it is moved out of the header fil=

e for some reason.

Post by Robert Richter
=20
I assume pci/host-generic is the latest now with this issue fixed as
the commit date is 2014-10-01 past you message above, right? So is it
ok to rebase our host controller driver onto pci/host-generic or will
there be further updates or any other branch that is newer?

You can rebase either on top of Bjorn's next branch or use linux-next. =
Hope to
see it in v3.18 soon.

Best regards,
Liviu

Post by Robert Richter
=20
Thanks,
=20
-Robert
=20

--=20
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
| I would like to |
| fix the world, |
| but they're not |
| giving me the |
\ source code! /
---------------
=C2=AF\_(=E3=83=84)_/=C2=AF

[Robert Richter]

Post by Robert Richter
I assume pci/host-generic is the latest now with this issue fixed as
the commit date is 2014-10-01 past you message above, right? So is it
ok to rebase our host controller driver onto pci/host-generic or will
there be further updates or any other branch that is newer?

You can rebase either on top of Bjorn's next branch or use linux-next. Hope to
see it in v3.18 soon.

Thanks Liviu. So I will use pci/host-generic which is what is in
pci/next:

d1e6dc91b532 arm64: Add architectural support for PCI

-Robert
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To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to majordomo-***@public.gmane.org
More majordomo info at http://vger.kernel.org/majordomo-info.html

[Liviu Dudau]

Post by Robert Richter

Post by Robert Richter
I assume pci/host-generic is the latest now with this issue fixed as
the commit date is 2014-10-01 past you message above, right? So is it
ok to rebase our host controller driver onto pci/host-generic or will
there be further updates or any other branch that is newer?

You can rebase either on top of Bjorn's next branch or use linux-next. Hope to
see it in v3.18 soon.

Thanks Liviu. So I will use pci/host-generic which is what is in
d1e6dc91b532 arm64: Add architectural support for PCI

Yes, that's the one.

Best regards,
Liviu

Post by Robert Richter
-Robert